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ltc2217 1 2217f 2217 ta01b ?30 ?20 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 frequency (mhz) amplitude (dbfs) 010 30 40 20 50 typical application applications 16-bit, 105msps low noise adc the ltc 2217 is a 105msps sampling 16-bit a/d converter designed for digitizing high frequency, wide dynamic range signals with input frequencies up to 400mhz. the input range of the adc is ? xed at 2.75v p-p . the ltc2217 is perfect for demanding communications applications, with ac performance that includes 81.3dbfs noise floor and 100db spurious free dynamic range (sfdr). ultra low jitter of 85fs rms allows undersampling of high input frequencies while maintaining excellent noise performance. maximum dc speci? cations include 3.5lsb inl, 1lsb dnl (no missing codes). the digital output can be either differential lvds or single-ended cmos. there are two format options for the cmos outputs: a single bus running at the full data rate or demultiplexed buses running at half data rate. a separate output power supply allows the cmos output swing to range from 0.5v to 3.6v. the enc + and enc C inputs may be driven differentially or single-ended with a sine wave, pecl, lvds, ttl or cmos inputs. an optional clock duty cycle stabilizer al- lows high performance at full speed with a wide range of clock duty cycles. telecommunications receivers cellular base stations spectrum analysis imaging systems ate sample rate: 105msps 81.3dbfs noise floor 100db sfdr sfdr >90db at 70mhz 85fs rms jitter 2.75v p-p input range 400mhz full power bandwidth s/h optional internal dither optional data output randomizer lvds or cmos outputs single 3.3v supply power dissipation: 1.19w clock duty cycle stabilizer pin compatible with ltc2208 64-pin (9mm 9mm) qfn package , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. patents pending. 64k point fft, f in = 4.9mhz, C1dbfs + s/h amp correction logic and shift register output drivers 16-bit pipelined adc core internal adc reference generator 1.575v common mode bias voltage clock/duty cycle control d15 d0 shdn dith mode lvds rand v cm analog input 2217 ta01 cmos or lvds 0.5v to 3.6v 3.3v 3.3v sense ognd ov dd 2.2 f 1 f 1 f 1 f 1 f v dd gnd adc control inputs ain + enc + ain enc of clkout features description
ltc2217 2 2217f the o denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) supply voltage (v dd ) ................................... ? 0.3v to 4v digital output ground voltage (ognd) ........ ? 0.3v to 1v analog input voltage (note 3) ..... ? 0.3v to (v dd + 0.3v) digital input voltage .................... ? 0.3v to (v dd + 0.3v) digital output voltage ................ ? 0.3v to (ov dd + 0.3v) power dissipation ............................................ 2000mw operating temperature range ltc2217c ................................................ 0c to 70c ltc2217i .............................................? 40c to 85c storage temperature range ..................? 65c to 150c digital output supply voltage (ov dd ) .......... ? 0.3v to 4v ov dd = v dd (notes 1 and 2) pin configuration absolute maximum ratings top view 65 sense 1 gnd 2 v cm 3 gnd 4 v dd 5 v dd 6 gnd 7 ain + 8 ain e 9 gnd 10 gnd 11 enc + 12 enc e 13 gnd 14 v dd 15 v dd 16 48 d11 + /da6 47 d11 e /da5 46 d10 + /da4 45 d10 e /da3 44 d9 + /da2 43 d9 e /da1 42 d8 + /da0 41 d8 e /clkouta 40 clkout + /clkoutb 39 clkout e /ofb 38 d7 + /db15 37 d7 e /db14 36 d6 + /db13 35 d6 e /db12 34 d5 + /db11 33 d5 e /db10 64 nc 63 rand 62 mode 61 lvds 60 of + /ofa 59 of e /da15 58 d15 + /da14 57 d15 /da13 56 d14 + /da12 55 d14 e e /da11 54 d13 + /da10 53 d13 e e /da9 52 d12 + /da8 51 d12 /da7 50 ognd 49 ov dd v dd 17 gnd 18 shdn 19 dith 20 d0 e /db0 21 do + /db1 22 d1 e /db2 23 d1 + /db3 24 d2 e /db4 25 d2 + /db5 26 d3 e /db6 27 d3 + /db7 28 d4 e /db8 29 d4 + /db9 30 ognd 31 ov dd 32 t jmax = 150c,
ltc2217 3 2217f the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) analog input symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 3.135v v dd 3.465v 2.75 v p-p v in, cm analog input common mode differential input (note 7) 1.2 1.575 1.8 v i in analog input leakage current 0v a in + , a in C v dd C1 1 a i sense sense input leakage current 0v sense v dd C3 3 a i mode mode pin pull-down current to gnd 10 a i lvds lvds pin pull-down current to gnd 10 a c in analog input capacitance sample mode enc + < enc C hold mode enc + > enc C 9.1 1.8 pf pf t ap sample-and-hold acquisition delay time 0.35 ns t jitter sample-and-hold aperture jitter 85 fs rms cmrr analog input common mode rejection ratio 1.2v < (a in + = a in C ) <1.8v 80 db bw-3db full power bandwidth r s < 25 1 400 mhz the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C1dbfs with 2.75v range unless otherwise noted. (note 4) dynamic accuracy symbol parameter conditions min typ max units snr signal-to-noise ratio 5mhz input 81.2 dbfs 15mhz input, t a = 25c 15mhz input 80.4 80.1 81.1 80.7 dbfs dbfs 30mhz input, t a = 25c 81.1 dbfs 70mhz input, t a = 25c 70mhz input 79.6 79.3 80.4 80.1 dbfs dbfs 140mhz input 78.8 dbfs sfdr spurious free dynamic range 2nd or 3rd harmonic 5mhz input 100 dbc 15mhz input, t a = 25c 15mhz input 88 87 100 99 dbc dbc 30mhz input 95 dbc 70mhz input, t a = 25c 70mhz input 85 83 92 88 dbc dbc 140mhz input 85 dbc sfdr spurious free dynamic range 4th harmonic or higher 5mhz input 105 dbc 15mhz input 93 105 dbc 30mhz input 105 dbc 70mhz input 93 103 dbc 140mhz input 95 dbc
ltc2217 4 2217f symbol parameter conditions min typ max units s/(n+d) signal-to-noise plus distortion ratio 5mhz input 81.2 dbfs 15mhz input, t a = 25c 15mhz input 79.9 79.7 81 80.6 dbfs dbfs 30mhz input 81.1 dbfs 70mhz input, t a = 25c 70mhz input 78.7 78.2 80 79.5 dbfs dbfs 140mhz input 78.8 dbfs sfdr spurious free dynamic range at C 25dbfs dither off 5mhz input 105 dbfs 15mhz input 105 dbfs 30mhz input 105 dbfs 70mhz input 105 dbfs 140mhz input 100 dbfs sfdr spurious free dynamic range at C 25dbfs dither on 5mhz input 115 dbfs 15mhz input 100 115 dbfs 30mhz input 115 dbfs 70mhz input 115 dbfs 140mhz input 110 dbfs imd intermodulation distortion f in1 = 14mhz, f in2 = 21mhz, C7dbfs f in1 = 67mhz, f in2 = 74mhz, C7dbfs 100 90 dbc dbc the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C1dbfs with 2.75v range unless otherwise noted. (note 4) dynamic accuracy the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) common mode bias characteristics parameter conditions min typ max units v cm output voltage i out = 0 1.475 1.575 1.675 v v cm output tempco i out = 0 60 ppm/c v cm line regulation 3.135v v dd 3.465v 2.4 mv/ v v cm output resistance | i out | 0.8ma 1.1 1
ltc2217 5 2217f the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) digital inputs and digital outputs symbol parameter conditions min typ max units encode inputs (enc + , enc C ) v id differential input voltage (note 7) 0.2 v v icm common mode input voltage internally set externally set (note 7) 1.2 1.6 3 v v r in input resistance (see figure 2) 6 k 1 c in input capacitance (note 7) 3 pf logic inputs v ih high level input voltage v dd = 3.3v 2v v il low level input voltage v dd = 3.3v 0.8 v i in digital input current v in = 0v to v dd 10 a c in digital input capacitance (note 7) 1.5 pf logic outputs (cmos mode) ov dd = 3.3v v oh high level output voltage v dd = 3.3v i o = C10a i o = C 200a 3.1 3.299 3.29 v v v ol low level output voltage v dd = 3.3v i o = 160a i o = 1.6ma 0.01 0.10 0.4 v v i source output source current v out = 0v C50 ma i sink output sink current v out = 3.3v 50 ma ov dd = 2.5v v oh high level output voltage v dd = 3.3v i o = C 200a 2.49 v v ol low level output voltage v dd = 3.3v i o = 1.60ma 0.1 v ov dd = 1.8v v oh high level output voltage v dd = 3.3v i o = C 200a 1.79 v v ol low level output voltage v dd = 3.3v i o = 1.60ma 0.1 v logic outputs (lvds mode) standard lvds v od differential output voltage 100 1 differential load 247 350 454 mv v os output common mode voltage 100 1 differential load 1.125 1.2 1.375 v low power lvds v od differential output voltage 100 1 differential load 125 175 250 mv v os output common mode voltage 100 1 differential load 1.125 1.2 1.375 v
ltc2217 6 2217f symbol parameter conditions min typ max units v dd analog supply voltage (note 8) 3.135 3.3 3.465 v p shdn shutdown power shdn = v dd 17 mw standard lvds output mode ov dd output supply voltage (note 8) 3 3.3 3.6 v i vdd analog supply current 365 430 ma i ovdd output supply current 75 90 ma p dis power dissipation 1450 1716 mw low power lvds output mode ov dd output supply voltage (note 8) 3 3.3 3.6 v i vdd analog supply current 363 430 ma i ovdd output supply current 42 50 ma p dis power dissipation 1335 1584 mw cmos output mode ov dd output supply voltage (note 8) 0.5 3.6 v i vdd analog supply current 360 430 ma p dis power dissipation 1190 1420 mw power requirements the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C1dbfs unless otherwise noted. (note 4) symbol parameter conditions min typ max units f s sampling frequency (note 8) 1 105 mhz t l enc low time duty cycle stabilizer off (note 7) duty cycle stabilizer on (note 7) 4.52 3.1 4.762 4.762 500 500 ns ns t h enc high time duty cycle stabilizer off (note 7) duty cycle stabilizer on (note 7) 4.52 3.1 4.762 4.762 500 500 ns ns lvds output mode (standard and low power) t d enc to data delay (note 7) 1.3 2.5 3.8 ns t c enc to clkout delay (note 7) 1.3 2.5 3.8 ns t skew data to clkout skew (t c -t d ) (note 7) C0.6 0 0.6 ns t rise output rise time 0.5 ns t fall output fall time 0.5 ns data latency data latency 7 cycles cmos output mode t d enc to data delay (note 7) 1.3 2.7 4 ns t c enc to clkout delay (note 7) 1.3 2.7 4 ns t skew data to clkout skew (t c -t d ) (note 7) C 0.6 0 0.6 ns data latency data latency full rate cmos demuxed 7 7 cycles cycles the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) timing characteristics
ltc2217 7 2217f timing diagram note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd, with gnd and ognd shorted (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: v dd = 3.3v, f sample = 105mhz, lvds outputs, differential enc + / enc C = 2v p-p sine wave with 1.6v common mode, input range = 2.75v p-p with differential drive, unless otherwise speci? ed. note 5: integral nonlinearity is de? ned as the deviation of a code from a best ? t straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 6: offset error is the offset voltage measured from C1/2lsb when the output code ? ickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2s complement output mode. note 7: guaranteed by design, not subject to test. note 8: recommended operating conditions. lvds output mode timing all outputs are differential and have lvds levels t h t d t c t l n ?7 n ?6 n ?5 n ?4 n ?3 analog input enc enc + clkout clkout + d0-d15, of 2217 td01 t ap n + 1 n + 2 n + 4 n + 3 n electrical characteristics
ltc2217 8 2217f t h t d t d t c t l n ?8 n ?6 n ?4 n ?7 n ?5 n ?3 enc enc + clkouta clkoutb da0-da15, ofa db0-db15, ofb 2217 td03 t ap analog input n + 1 n + 2 n + 4 n + 3 n t ap analog input t h t d t c t l n ?7 n ?6 n ?5 n ?4 n ?3 enc enc + clkouta clkoutb da0-da15, ofa db0-db15, ofb 2217 td02 high impedance n + 1 n + 2 n + 4 n + 3 n demultiplexed cmos output mode timing all outputs are single-ended and have cmos levels full-rate cmos output mode timing all outputs are single-ended and have cmos levels timing diagrams
ltc2217 9 2217f 2217 g07 ?30 ?20 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 01020304050 frequency (mhz) am p litude (dbfs) 2217 g08 ?30 ?20 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 0 1020304050 frequency (mhz) am p litude (dbfs) 2217 g09 ?30 ?20 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 0 1020304050 frequency (mhz) am p litude (dbfs) ?.0 ?.5 ?.0 ?.5 0.0 0.5 1.0 1.5 2.0 0 16384 32768 49152 65536 output code inl error (lsb) 2217 g01 ?.0 ?.5 ?.0 ?.5 0.0 0.5 1.0 1.5 2.0 0 16384 32768 49152 65536 output code inl error (lsb) 2217 g02 ?.0 ?.8 ?.6 ?.4 ?.2 0.0 0.2 0.4 0.6 0.8 1.0 0 16384 32768 49152 65536 output code dnl error (lsb) 2217 g03 integral nonlinearity (inl) vs output code - dither off integral nonlinearity (inl) vs output code - dither on 64k point fft, f in = 15.1mhz, C1dbfs 64k point fft, f in = 4.9mhz, C1dbfs 64k point fft, f in = 15.1mhz, C20dbfs, dither off ac grounded input histogram typical performance characteristics 64k point 2-tone fft, f in = 14.25mhz and 21.5mhz, C7dbfs 64k point fft, f in = 15.1mhz, C20dbfs, dither on differential nonlinearity (dnl) vs output code 2217 g04 0 2000 4000 6000 8000 10000 12000 14000 32736 32745 32754 output code count 2217 g05 ?30 ?20 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 01020304050 frequency (mhz) am p litude (dbfs) 2217 g06 ?30 ?20 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 01020304050 frequency (mhz) am p litude (dbfs)
ltc2217 10 2217f snr vs input level, f in = 15.2mhz 64k point fft, f in = 28.7mhz, C1dbfs 64k point fft, f in = 30.1mhz, C20dbfs, dither on 64k point fft, f in = 70.2mhz, C1dbfs 64k point fft, f in = 70.1mhz, C20dbfs, dither off sfdr vs input level, f in = 15.2mhz, dither on 64k point fft, f in = 70.1mhz, C10dbfs, dither off typical performance characteristics sfdr vs input level, f in = 15.2mhz, dither off 64k point 2-tone fft, f in = 14.25mhz and 21.5mhz, C25dbfs, dither on ?30 ?20 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 01020304050 frequency (mhz) am p litude (dbfs) 2217 g10 30 40 50 60 70 80 90 100 110 120 130 140 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 input level (dbfs) sfd r (d bc a n d d bfs) 2217 g11 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 30 40 50 60 70 80 90 100 110 120 130 140 input level (dbfs) sfd r (d bc a n d d bfs) 2217 g12 2217 g13 78 79 80 81 82 input level (dbfs) snr (dbfs) ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 2217 g14 ?30 ?20 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 01020304050 frequency (mhz) am p litude (dbfs) 2217 g15 ?30 ?20 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 01020304050 frequency (mhz) am p litude (dbfs) 2217 g16 ?30 ?20 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 01020304050 frequency (mhz) am p litude (dbfs) 2217 g17 ?30 ?20 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 01020304050 frequency (mhz) am p litude (dbfs) 2217 g18 ?30 ?20 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 0 1020304050 frequency (mhz) am p litude (dbfs)
ltc2217 11 2217f snr vs input level, f in = 70.5mhz 64k point 2-tone fft, f in = 67.2mhz and 74.4mhz, C7dbfs 64k point 2-tone fft, f in = 67.2mhz and 74.4mhz, C15dbfs, dither on 64k point fft, f in = 70.1mhz, C20dbfs, dither on sfdr vs input level, f in = 70.5mhz, dither off sfdr vs input level, f in = 70.5mhz, dither on 64k point fft, f in = 140.1mhz, C20dbfs, dither on typical performance characteristics 64k point 2-tone fft, f in = 67.2mhz and 74.4mhz, C25dbfs, dither on 64k point fft, f in = 140.5mhz, C1dbfs 2217 g19 ?30 ?20 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 01020304050 frequency (mhz) am p litude (dbfs) 2217 g20 30 40 50 60 70 80 90 100 110 120 130 140 input level (dbfs) sfd r (d bc a n d d bfs) ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 2217 g21 30 40 50 60 70 80 90 100 110 120 130 140 input level (dbfs) sfd r (d bc a n d d bfs) ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 2217 g22 78 79 80 81 82 input level (dbfs) snr (dbfs) ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 2217 g23 ?30 ?20 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 01020304050 frequency (mhz) amplitud e (dbfs) 2217 g24 ?30 ?20 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 01020304050 frequency (mhz) am p litude (dbfs) 2217 g25 ?30 ?20 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 01020304050 frequency (mhz) am p litude (dbfs) 2217 g26 ?30 ?20 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 01020304050 frequency (mhz) am p litude (dbfs) 2217 g27 ?30 ?20 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 0 1020304050 frequency (mhz) am p litude (dbfs)
ltc2217 12 2217f snr vs input level, f in = 140.5mhz sfdr (hd2 and hd3) vs input frequency snr vs input frequency sfdr vs input level, f in = 140.5mhz, dither on snr and sfdr vs sample rate, f in = 5.2mhz typical performance characteristics sfdr vs input level, f in = 140.5mhz, dither off snr and sfdr vs supply voltage (v dd ), f in = 5.1mhz i vdd vs sample rate and supply voltage, f in = 5mhz, C1dbfs snr and sfdr vs clock duty cycle, f in = 5.2mhz 2217 g28 input level (dbfs) sfdr (dbc and dbfs) 30 40 50 60 70 80 90 100 110 120 130 140 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 2217 g29 30 40 50 60 70 80 90 100 110 120 130 140 input level (dbfs) sfd r (d bc a n d d bfs) ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 2217 g30 78 79 80 81 82 input level (dbfs) snr (dbfs) ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 2217 g31 0 50 100 150 200 250 input frequency (mhz) sfdr, hd2, hd3 (dbc) hd3 hd2 70 75 80 85 90 95 100 105 110 sfdr 2217 g32 76 77 78 79 80 81 82 0 50 100 150 200 250 input frequency (mhz) snr (dbfs) 2217 g33 70 75 80 85 90 95 100 105 110 0 40 80 120 160 sample rate (msps) snr (dbfs) and sfdr (dbc) snr sfdr limit 2217 g34 70 75 80 85 90 95 100 105 110 2.8 3.0 3.2 3.4 3.6 supply voltage (v) snr (dbfs) and sfdr (dbc) sfdr snr lower limit upper limit 2217 g35 sample rate (msps) 0 50 100 150 200 i vdd (ma) 300 325 350 375 400 425 450 v dd = 3.465v v dd = 3.135v v dd = 3.3v 2217 g36 60 70 80 90 100 110 30 40 50 60 70 duty cycle (%) sn r (d bfs) a n d sfd r (d bc) sfdr dcs off snr dcs off sfdr dcs on snr dcs on
ltc2217 13 2217f 2217 g37 0.995 0.996 0.997 0.998 0.999 1 1.001 1.002 1.003 1.004 1.005 temperature ( c) normalized full scale ?0 ?0 0 20 40 60 80 2217 g38 ? ? ? ? ? 0 1 2 3 4 5 ?0 ?0 0 20 40 60 80 temperature ( c) offset voltage (mv) 2217 g39 0.995 0.996 0.997 0.998 0.999 1 1.001 1.002 1.003 1.004 1.005 temperature ( c) normalized full scale ?0 ?0 0 20 40 60 80 2217 g40 ? ? ? ? ? 0 1 2 3 4 5 temperature ( c) offset voltage (mv) ?0 ?0 0 20 40 60 80 2217 g41 60 65 70 75 80 85 90 95 100 105 110 0.5 0.75 1 1.25 1.5 1.75 2 analog input common mode voltage (v) sfdr (dbc) 70mhz 5mhz input offset voltage vs temperature, internal reference, 5 units normalized full scale vs temperature, external reference, 5 units input offset voltage vs temperature, external reference, 5 units typical performance characteristics normalized full scale vs temperature, internal reference, 5 units sfdr vs analog input common mode voltage, 5mhz and 70mhz, C1dbfs mid-scale settling after wake up from shutdown or starting encode clock full-scale settling after wake up from shutdown or starting encode clock 0 300 600 900 1200 1500 time after wake-up or clock start ( s) full-scale error (%) ?.5 ?.4 ?.3 ?.2 ?.1 0.0 0.1 0.2 0.3 0.4 0.5 clock start wake-up 2217 g42 time after wake-up or clock start ( s) full-scale error (%) ?.5 ?.4 ?.3 ?.2 ?.1 0.0 0.1 0.2 0.3 0.4 0.5 clock start wake-up 0 400 800 1200 1600 2000 2217 g43
ltc2217 14 2217f for cmos mode. full rate or demultiplexed sense (pin 1): reference mode select and external reference input. tie sense to v dd to select the internal 2.5v bandgap reference. an external reference of 2.5v or 1.25v may be used; both reference values will set a full scale adc range of 2.75v. gnd (pins 2, 4, 7, 10, 11, 14, 18): adc power ground. v cm (pin 3): 1.575v output. optimum voltage for input com- mon mode. must be bypassed to ground with a minimum of 2.2f. ceramic chip capacitors are recommended. v dd (pins 5, 6, 15, 16, 17): 3.3v analog supply pin. bypass to gnd with 1f ceramic chip capacitors. a in + (pin 8): positive differential analog input. a in C (pin 9): negative differential analog input. enc + (pin 12): positive differential encode input. the sampled analog input is held on the rising edge of enc + . internally biased to 1.6v through a 6.2k 1 resistor. output data can be latched on the rising edge of enc + . enc C (pin 13): negative differential encode input. the sampled analog input is held on the falling edge of enc C . internally biased to 1.6v through a 6.2k 1 resistor. by- pass to ground with a 0.1f capacitor for a single-ended encode signal. shdn (pin 19): power shutdown pin. shdn = low results in normal operation. shdn = high results in powered down analog circuitry and the digital outputs are placed in a high impedance state. dith (pin 20): internal dither enable pin. dith = low disables internal dither. dith = high enables internal dither. refer to internal dither section of this data sheet for details on dither operation. db0-db15 (pins 21-30 and 33-38): digital outputs, b bus. db15 is the msb. active in demultiplexed mode. the b bus is in high impedance state in full rate cmos mode. ognd (pins 31 and 50): output driver ground. ov dd (pins 32 and 49): positive supply for the output drivers. bypass to ground with 1f capacitor. ofb (pin 39): over/under flow digital output for the b bus. ofb is high when an over or under ? ow has occurred on the b bus. at high impedance state in full rate cmos mode. clkoutb (pin 40): data valid output. clkoutb will toggle at the sample rate in full rate cmos mode or at 1/2 the sample rate in demultiplexed mode. latch the data on the falling edge of clkoutb. clkouta (pin 41): inverted data valid output. clkouta will toggle at the sample rate in full rate cmos mode or at 1/2 the sample rate in demultiplexed mode. latch the data on the rising edge of clkouta. da0-da15 (pins 42-48 and 51-59): digital outputs, a bus. da15 is the msb. output bus for full rate cmos mode and demultiplexed mode. ofa (pin 60): over/under flow digital output for the a bus. ofa is high when an over or under ? ow has occurred on the a bus. lvds (pin 61): data output mode select pin. connecting lvds to 0v selects full rate cmos mode. connecting lvds to 1/3v dd selects demultiplexed cmos mode. connecting lvds to 2/3v dd selects low power lvds mode. connect- ing lvds to v dd selects standard lvds mode. mode (pin 62): output format and clock duty cycle stabilizer selection pin. connecting mode to 0v selects offset binary output format and disables the clock duty cycle stabilizer. connecting mode to 1/3v dd selects offset binary output format and enables the clock duty cycle sta- bilizer. connecting mode to 2/3v dd selects 2s complement output format and enables the clock duty cycle stabilizer. connecting mode to v dd selects 2s complement output format and disables the clock duty cycle stabilizer. rand (pin 63): digital output randomization selection pin. rand low results in normal operation. rand high selects d1-d15 to be exclusive-ored with d0 (the lsb). the output can be decoded by again applying an xor operation between the lsb and all other bits. this mode of operation reduces the effects of digital output interference. nc (pin 64): not connected internally. for pin compatibility with the ltc2208 this pin should be connected to gnd or v dd as required. otherwise no connection. gnd (exposed pad): adc power ground. the exposed pad on the bottom of the package must be soldered to ground. pin functions
ltc2217 15 2217f for lvds mode. standard or low power sense (pin 1): reference mode select and external reference input. tie sense to v dd to select the internal 2.5v bandgap reference. an external reference of 2.5v or 1.25v may be used; both reference values will set a full scale adc range of 2.75v. gnd (pins 2, 4, 7, 10, 11, 14, 18): adc power ground. v cm (pin 3): 1.575v output. optimum voltage for input common mode. must be bypassed to ground with a minimum of 2.2f. ceramic chip capacitors are recom- mended. v dd (pins 5, 6, 15, 16, 17): 3.3v analog supply pin. bypass to gnd with 1f ceramic chip capacitors. a in + (pin 8): positive differential analog input. a in C (pin 9): negative differential analog input. enc + (pin 12): positive differential encode input. the sampled analog input is held on the rising edge of enc + . internally biased to 1.6v through a 6.2k 1 resistor. output data can be latched on the rising edge of enc + . enc C (pin 13): negative differential encode input. the sampled analog input is held on the falling edge of enc C . internally biased to 1.6v through a 6.2k 1 resistor. by- pass to ground with a 0.1f capacitor for a single-ended encode signal. shdn (pin 19): power shutdown pin. shdn = low results in normal operation. shdn = high results in powered down analog circuitry and the digital outputs are set in high impedance state. dith (pin 20): internal dither enable pin. dith = low disables internal dither. dith = high enables internal dither. refer to internal dither section of the data sheet for details on dither operation. d0 C /d0 + to d15 C /d15 + (pins 21-30, 33-38, 41-48 and 51-58): lvds digital outputs. all lvds outputs require differential 100 1 termination resistors at the lvds receiver. d15 + /d15 C is the msb. ognd (pins 31 and 50): output driver ground. ov dd (pins 32 and 49): positive supply for the output drivers. bypass to ground with 0.1f capacitor. clkout C /clkout + (pins 39 and 40): lvds data valid 0utput. latch data on the rising edge of clkout + , falling edge of clkout C . of C /of + (pins 59 and 60): over/under flow digital output of is high when an over or under ? ow has occurred. lvds (pin 61): data output mode select pin. connecting lvds to 0v selects full rate cmos mode. connecting lvds to 1/3v dd selects demultiplexed cmos mode. connecting lvds to 2/3v dd selects low power lvds mode. connect- ing lvds to v dd selects standard lvds mode. mode (pin 62): output format and clock duty cycle stabilizer selection pin. connecting mode to 0v selects offset binary output format and disables the clock duty cycle stabilizer. connecting mode to 1/3v dd selects offset binary output format and enables the clock duty cycle sta- bilizer. connecting mode to 2/3v dd selects 2s complement output format and enables the clock duty cycle stabilizer. connecting mode to v dd selects 2s complement output format and disables the clock duty cycle stabilizer. rand (pin 63): digital output randomization selection pin. rand low results in normal operation. rand high selects d1-d15 to be exclusive-ored with d0 (the lsb). the output can be decoded by again applying an xor operation between the lsb and all other bits. the mode of operation reduces the effects of digital output interference. nc (pin 64): not connected internally. for pin compat- ibility with the ltc2208 this pin should be connected to gnd or v dd as required. otherwise no connection. gnd (exposed pad pin 65): adc power ground. the exposed pad on the bottom of the package must be sol- dered to ground. pin functions
ltc2217 16 2217f adc clocks differential input low jitter clock driver dither signal generator first pipelined adc stage fifth pipelined adc stage fourth pipelined adc stage second pipelined adc stage enc + enc correction logic and shift register dith m0de ognd clkout+ clkout of + of d15 + d15 ov dd d0 + d0 2217 f01 input s/h a in a in + third pipelined adc stage output drivers control logic shdn rand lvds v dd gnd pga sense v cm buffer adc reference voltage reference range select figure 1. functional block diagram block diagram
ltc2217 17 2217f dynamic performance signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n+d)] is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the adc output. the output is band lim- ited to frequencies above dc to below half the sampling frequency (nyquist frequency). signal-to-noise ratio the signal-to-noise (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components, except the ? rst ? ve harmonics. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency (nyquist frequency). thd is expressed as: thd log vvv v v n = +++ () ? ? ? ? ? ? ? ? ? ? ?0 2 2 3 2 4 22 1 where v 1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the second through nth harmonics. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. for example, the 3rd order imd terms include (2fa + fb), (fa + 2fb), (2fa - fb) and (fa - 2fb). the 3rd order imd is de? ned as the ratio of the rms value of either input tone to the rms value of the largest 3rd order imd product. spurious free dynamic range (sfdr) the ratio of the rms input signal amplitude to the rms value of the peak spurious spectral component expressed in dbc. sfdr may also be calculated relative to full scale and expressed in dbfs. full power bandwidth the full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db from a full scale input signal. aperture delay time the time from when a rising enc + equals the enc C voltage to the instant that the input signal is held by the sample- and-hold circuit. aperture delay jitter the variation in the aperture delay time from conversion to conversion. this random variation will result in noise when sampling an ac input. the signal-to-noise ratio term due to the jitter alone will be: snr jitter = C 20log (2 / ? f in ? t jitter ) this formula states snr due to jitter alone at any amplitude in terms of dbc. operation
ltc2217 18 2217f converter operation the ltc2217 is a cmos pipelined multistep converter with a low noise front-end. as shown in figure 1, the converter has ? ve pipelined adc stages; a sampled analog input will result in a digitized value seven cycles later (see the timing diagram section). the analog input is differential for improved common mode noise immunity and to maximize the input range. additionally, the differential input drive will reduce even order harmonics of the sample and hold circuit. the encode input is also differential for improved common mode noise immunity. the ltc2217 has two phases of operation, determined by the state of the differential enc + /enc C input pins. for brevity, the text will refer to enc + greater than enc C as enc high and enc + less than enc C as enc low. each pipelined stage shown in figure 1 contains an adc, a reconstruction dac and an interstage ampli? er. in operation, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the dac to produce a residue. the residue is ampli? ed and output by the residue ampli? er. successive stages oper- ate out of phase so that when odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. when enc is low, the analog input is sampled differen- tially directly onto the input sample-and-hold capacitors, inside the input s/h shown in the block diagram. at the instant that enc transitions from low to high, the voltage on the sample capacitors is held. while enc is high, the held input voltage is buffered by the s/h ampli? er which drives the ? rst pipelined adc stage. the ? rst stage acquires the output of the s/h ampli? er during the high phase of enc. when enc goes back low, the ? rst stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when enc goes high, the second stage produces its residue which is acquired by the third stage. an identical process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the ? fth stage for ? nal evaluation. each adc stage following the ? rst has additional range to accommodate ? ash and ampli? er offset errors. results from all of the adc stages are digitally delayed such that the results can be properly combined in the correction logic before being sent to the output buffer. sample/hold operation and input drive sample/hold operation figure 2 shows an equivalent circuit for the ltc2217 cmos differential sample and hold. the differential analog inputs are sampled directly onto sampling capacitors (c sample ) through nmos transitors. the capacitors shown attached to each input (c parasitic ) are the summation of all other capacitance associated with each input. during the sample phase when enc is low, the nmos transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. when enc transitions from low to high, the sampled input voltage is held on the sampling capacitors. during the hold phase when enc is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the adc core for processing. as enc transitions for high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. if the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. if the figure 2. equivalent input circuit v dd ltc2217 a in + 2217 f02 v dd a in enc enc + 1.6v 6k v dd 1.6v 6k r parasitic 3 r parasitic 3 c parasitic 1.8pf c sample 7.3pf c sample 7.3pf c parasitic 1.8pf r on 20 r on 20 applications information
ltc2217 19 2217f input change is large, such as the change seen with input frequencies near nyquist, then a larger charging glitch will be seen. common mode bias the adc sample-and-hold circuit requires differential drive to achieve speci? ed performance. each input should swing 0.6875v for the 2.75v range, around a common mode voltage of 1.575v. the v cm output pin (pin 3) is designed to provide the common mode bias level. v cm can be tied directly to the center tap of a transformer to set the dc input level or as a reference level to an op amp differential driver circuit. the v cm pin must be bypassed to ground close to the adc with 2.2f or greater. input drive impedance as with all high performance, high speed adcs the dynamic performance of the ltc2217 can be in? uenced by the input drive circuitry, particularly the second and third harmonics. source impedance and input reactance can in? uence sfdr. at the falling edge of enc the sample and hold circuit will connect the sampling capacitor to the input pin and start the sampling period. the sampling period ends when enc rises, holding the sampled input on the sampling capacitor. ide- ally, the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2 ? f encode ); however, this is not always possible and the incomplete settling may degrade the sfdr. the sam- pling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. for the best performance it is recommended to have a source impedance of 100 1 or less for each input. the source impedance should be matched for the differential inputs. poor matching will result in higher even order harmonics, especially the second. input drive circuits input filtering a ? rst-order rc low-pass ? lter at the input of the adc can serve two functions: limit the noise from input circuitry and provide isolation from adc s/h switching. the ltc2217 has a very broadband s/h circuit, dc to 400mhz; it can be used in a wide range of applications; therefore, it is not possible to provide a single recommended rc ? lter. figures 3 and 4 show two examples of input rc ? ltering for two ranges of input frequencies. in general it is desirable to make the capacitors as large as can be toleratedthis will help suppress random noise as well as noise coupled from the digital circuitry. the ltc2217 does not require any input ? lter to achieve data sheet speci? cations; however, no ? ltering will put more stringent noise requirements on the input drive circuitry. transformer coupled circuits figure 3 shows the ltc2217 being driven by an rf trans- former with a center-tapped secondary. the secondary center tap is dc biased with v cm , setting the adc input signal at its optimum dc level. figure 3 shows a 1:1 turns ratio transformer. other turns ratios can be used; however, as the turns ratio increases so does the impedance seen by the adc. source impedance greater than 50 1 can reduce the input bandwidth and increase high frequency distor- tion. a disadvantage of using a transformer is the loss of low frequency response. most small rf transformers have poor performance at frequencies below 1mhz. center-tapped transformers provide a convenient means of dc biasing the secondary; however, they often show poor balance at high input frequencies, resulting in large 2nd order harmonics. figure 3. single-ended to differential conversion using a transformer. recommended for input frequencies from 5mhz to 100mhz 35 5 35 10 10 5 5 0.1 f a in + a in 8.2pf 2.2 f 8.2pf 8.2pf v cm t1 t1 = ma/com etc1-1t resistors, capacitors are 0402 package size except 2.2 f 2217 f03 ltc2217 applications information
ltc2217 20 2217f figure 4 shows transformer coupling using a transmis- sion line balun transformer. this type of transformer has much better high-frequency response and balance than ? ux coupled center-tap transformers. coupling capacitors are added at the ground and input primary terminals to allow the secondary terminals to be biased at 1.575v. figure 5. dc coupled input with differential ampli? er 0.1 f a in + a in 4.7pf 2.2 f 4.7pf 4.7pf v cm analog input 0.1 f 0.1 f 5 25 25 5 10 10 t1 1:1 t1 = ma/com etc1-1-13 resistors, capacitors are 0402 package size except 2.2 f 2217 f04 ltc2217 5 figure 4. using a transmission line balun transformer. recommended for input frequencies from 100mhz to 250mhz + + a in + a in 2.2 f 12pf 12pf v cm analog input 2217 f05 cm amplifier = ltc6600-20, ltc1993, etc. high speed differential amplifier ltc2217 25 25 pga 1.575v sense v cm buffer internal adc reference range select and gain control 2.5v bandgap reference 2.2 f tie to v dd to use internal 2.5v reference or input an external 2.5v reference or input an external 1.25v reference 2217 f06 figure 6. reference circuit reference, tie the sense pin to v dd . to use an external reference, simply apply either a 1.25v or 2.5v reference voltage to the sense input pin. both 1.25v and 2.5v ap- plied to sense will result in a full scale range of 2.75v p-p . a 1.575v output, v cm , is provided for a common mode bias for input drive circuitry. an external bypass capacitor is required for the v cm output. this provides a high frequency low impedance path to ground for internal and external circuitry. this is also the compensation capacitor for the reference; which will not be stable without this capacitor. the minimum value required for stability is 2.2f. direct coupled circuits figure 5 demonstrates the use of a differential ampli? er to convert a single ended input signal into a differential input signal. the advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of any op amp or closed-loop ampli? er will de- grade the adc sfdr at high input frequencies. additionally, wideband op amps or differential ampli? ers tend to have high noise. as a result, the snr will be degraded unless the noise bandwidth is limited prior to the adc input. reference operation figure 6 shows the ltc2217 reference circuitry consisting of a 2.5v bandgap reference, a programmable gain ampli- ? er and control circuit. the ltc2217 has three modes of reference operation: internal reference, 1.25v external reference or 2.5v external reference. to use the internal applications information
ltc2217 21 2217f the internal programmable gain ampli? er provides the internal reference voltage for the adc. this ampli? er has very stringent settling requirements and therefore is not accessible for external use. the sense pin can be driven 5% around the nominal 2.5v or 1.25v external reference inputs. this adjustment range can be used to trim the adc gain error or other system gain errors. when selecting the internal reference, the sense pin should be tied to v dd as close to the converter as possible. if the sense pin is driven externally it should be bypassed to ground as close to the device as possible with 1f ceramic capacitor. figure 7. a 2.75v range adc with an external 2.5v reference v cm sense 1.575v 3.3v 2.2 f 2.2 f 1 f 2217 f07 ltc1461-2.5 2 6 4 ltc2217 3. if the adc is clocked with a ? xed-frequency sinusoidal signal, ? lter the encode signal to reduce wideband noise. 4. balance the capacitance and series resistance at both encode inputs such that any coupled noise will appear at both inputs as common mode noise. the encode inputs have a common mode range of 1.2v to v dd . each input may be driven from ground to v dd for single-ended drive. driving the encode inputs the noise performance of the ltc2217 can depend on the encode signal quality as much as on the analog input. the encode inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. each input is biased through a 6k resistor to a 1.6v bias. the bias resistors set the dc operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. any noise present on the encode signal will result in ad- ditional aperture jitter that will be rms summed with the inherent adc aperture jitter. in applications where jitter is critical (high input frequen- cies), take the following into consideration: 1. differential drive should be used. 2. use as large an amplitude possible. if using trans- former coupling, use a higher turns ratio to increase the amplitude. figure 8a. equivalent encode input circuit v dd ltc2217 2217 f08a v dd enc enc + 1.6v 1.6v 6k 6k to internal adc clock drivers v dd figure 8b. balun-driven encode 50 100 8.2pf 0.1 f 0.1 f 0.1 f t1 t1 = ma/com etc1-1-13 resistors and capacitors are 0402 package size 50 ltc2217 2217 f08b enc enc + applications information
ltc2217 22 2217f the lower limit of the ltc2217 sample rate is determined by droop affecting the sample and hold circuits. the pipelined architecture of this adc relies on storing analog signals on small valued capacitors. junction leakage will discharge the capacitors. the speci? ed minimum operating frequency for the ltc2217 is 1msps. digital outputs digital output modes the ltc2217 can operate in four digital output modes: standard lvds, low power lvds, full rate cmos, and demultiplexed cmos. the lvds pin selects the mode of operation. this pin has a four level logic input, centered at 0, 1/3v dd , 2/3v dd and v dd . an external resistor divider can be used to set the 1/3v dd and 2/3v dd logic levels. table 1 shows the logic states for the lvds pin. table 1. lvds pin function lvds digital output mode 0v(gnd) full-rate cmos 1/3v dd demultiplexed cmos 2/3v dd low power lvds v dd lvds digital output buffers (cmos modes) figure 11 shows an equivalent circuit for a single output buffer in cmos mode, full-rate or demultiplexed. each buffer is powered by ov dd and ognd, isolated from the adc power and ground. the additional n-channel transistor in the output driver allows operation down to low voltages. the internal resistor in series with the output makes the output appear as 50 1 to external circuitry and eliminates the need for external damping resistors. as with all high speed/high resolution converters, the digital output loading can affect the performance. the digital outputs of the ltc2217 should drive a minimum capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. the output should be buffered with a device such as a alvch16373 cmos latch. for full speed operation the capacitive load should be kept under 10pf. a resistor in series with the 2217 f10 enc enc + 3.3v 3.3v d0 q0 q0 mc100lvelt22 130 130 83 83 ltc2217 figure 10. enc drive using a cmos to pecl translator maximum and minimum encode rates the maximum encode rate for the ltc2217 is 105msps. for the adc to operate properly the encode signal should have a 50% (5%) duty cycle. each half cycle must have at least 4.5ns for the adc internal circuitry to have enough settling time for proper operation. achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as pecl or lvds. when using a single-ended encode signal asymmetric rise and fall times can result in duty cycles that are far from 50%. an optional clock duty cycle stabilizer can be used if the input clock does not have a 50% duty cycle. this circuit uses the rising edge of enc pin to sample the analog input. the falling edge of enc is ignored and an internal falling edge is generated by a phase-locked loop. the input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the pll to lock onto the input clock. to use the clock duty cycle stabilizer, the mode pin must be connected to 1/3v dd or 2/3v dd using external resistors. figure 9. single-ended enc drive, not recommended for low jitter 2217 f09 enc 1.6v v threshold = 1.6v enc + 0.1 f ltc2217 applications information
ltc2217 23 2217f resistor, even if the signal is not used (such as of + /of C or clkout + /clkout C ). to minimize noise the pc board traces for each lvds output pair should be routed close together. to minimize clock skew all lvds pc board traces should have about the same length. in low power lvds mode 1.75ma is steered between the differential outputs, resulting in 175mv at the lvds receivers 100 1 termination resistor. the output com- mon mode voltage is 1.20v, the same as standard lvds mode. data format the ltc2217 parallel digital output can be selected for offset binary or 2s complement format. the format is selected with the mode pin. this pin has a four level logic input, centered at 0, 1/3v dd , 2/3v dd and v dd . an external resistor divider can be user to set the 1/3v dd and 2/3v dd logic levels. table 2 shows the logic states for the mode pin. table 2. mode pin function mode output format clock duty cycle stabilizer 0(gnd) offset binary off 1/3v dd offset binary on 2/3v dd 2s complement on v dd 2s complement off 2217 f11 ov dd v dd v dd 0.1 f typical data output ognd ov dd 0.5v to 3.6v predriver logic data from latch 43 ltc2217 figure 11. equivalent circuit for a digital output buffer output may be used, but is not required since the adc has a series resistor of 43 1 on-chip. lower ov dd voltages will also help reduce interference from the digital outputs. digital output buffers (lvds modes) figure 12 shows an equivalent circuit for an lvds output pair. a 3.5ma current is steered from out + to out C or vice versa, which creates a 350mv differential voltage across the 100 1 termination resistor at the lvds receiver. a feedback loop regulates the common mode output volt- age to 1.20v. for proper operation each lvds output pair must be terminated with an external 100 1 termination 2217 f12 3.5ma 1.20v lvds receiver ognd 10k 10k v dd v dd 0.1 f ov dd 3.3v predriver logic data from latch + ov dd ov dd 43 43 100 ltc2217 figure 12. equivalent output buffer in lvds mode applications information
ltc2217 24 2217f over? ow bit an over? ow output bit (of) indicates when the converter is over-ranged or under-ranged. in cmos mode, a logic high on the ofa pin indicates an over? ow or under? ow on the a data bus, while a logic high on the ofb pin indicates an over? ow on the b data bus. in lvds mode, a differ- ential logic high on of + /of C pins indicates an over? ow or under? ow. output clock the adc has a delayed version of the encode input avail- able as a digital output, clkout. the clkout pin can be used to synchronize the converter data to the digital system. this is necessary when using a sinusoidal en- code. in both cmos modes, a bus data will be updated as clkouta falls and clkoutb rises. in demultiplexed cmos mode the b bus data will be updated as clkouta falls and clkoutb rises. in full rate cmos mode, only the a data bus is active; data may be latched on the rising edge of clkouta or the falling edge of clkoutb. in demultiplexed cmos mode clkouta and clkoutb will toggle at 1/2 the frequency of the encode signal. both the a bus and the b bus may be latched on the rising edge of clkouta or the falling edge of clkoutb. digital output randomizer interference from the adc digital outputs is sometimes unavoidable. interference from the digital outputs may be from capacitive or inductive coupling, or coupling through the ground plane. even a tiny coupling factor can result in discernible unwanted tones in the adc output spectrum. by randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized, trading a slight increase in the noise ? oor for a large reduction in unwanted tone amplitude. the digital output is randomized by applying an exclu- sive-or logic operation between the lsb and all other data output bits. to decode, the reverse operation is applied; that is, an exclusive-or operation is applied between the lsb and all other bits. the lsb, of and clkout output are not affected. the output randomizer function is active when the rand pin is high. output driver power separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. the power supply for the digital output buffers, ov dd , should be tied to the same power supply as for the logic being driven. for example, if the converter is driving a dsp powered by a 1.8v supply, then ov dd should be tied to that same 1.8v supply. in cmos mode ov dd can be powered with any logic voltage up to the 3.6v. ognd can be powered with any voltage from ground up to 1v and must be less than ov dd . the logic outputs will swing between ognd and ov dd . in lvds mode, ov dd should be connected to a 3.3v supply and ognd should be connected to gnd. figure 13. functional equivalent of digital output randomizer clkout of d15 d0 d14 d0 d2 d0 d1 d0 d0 d0 d1 rand = high, scramble enabled d2 d14 d15 of clkout rand 2217 f13 ltc2217 applications information
ltc2217 25 2217f figure 14. descrambling a scrambled digital output d1 d0 d2 d14 d15 pc board fpga clkout of d15 d0 d14 d0 d2 d0 d1 d0 d0 2217 f14 ltc2217 internal dither the ltc2217 is a 16-bit adc with a very linear transfer function; however, at low input levels even slight imperfec- tions in the transfer function will result in unwanted tones. small errors in the transfer function are usually a result of adc element mismatches. an optional internal dither mode can be enabled to randomize the input location on the adc transfer curve, resulting in improved sfdr for low signal levels. as shown in figure 15, the output of the sample-and-hold ampli? er is summed with the output of a dither dac. the dither dac is driven by a long sequence pseudo-random number generator; the random number fed to the dither dac is also subtracted from the adc result. if the dither dac is precisely calibrated to the adc, very little of the dither signal will be seen at the output. the dither signal that does leak through will appear as white noise. the dither dac is calibrated to result in typically less than 0.5db elevation in the noise ? oor of the adc as compared to the noise ? oor with dither off, when a suitable input termination is provided (see demo board schematic dc996b). figure 15. functional equivalent block diagram of internal dither circuit + ain ain + s/h amp digital summation output drivers multibit deep pseudo-random number generator 16-bit pipelined adc core precision dac clock/duty cycle control clkout of d15 d0 enc dither enable high = dither on low = dither off dith enc analog input 2217 f15 ltc2217 applications information
ltc2217 26 2217f grounding and bypassing the ltc2217 requires a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. the pinout of the ltc2217 has been optimized for a ? owthrough layout so that the interaction between inputs and digital outputs is minimized. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd, v cm , and ov dd pins. bypass capacitors must be located as close to the pins as possible. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the ltc2217 differential inputs should run parallel and close to each other. the input traces should be as short as possible to minimize capacitance and to minimize noise pickup. heat transfer most of the heat generated by the ltc2217 is transferred from the die through the bottom-side exposed pad. for good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the pc board. it is critical that the exposed pad and all ground pins are connected to a ground plane of suf? cient area with as many vias as possible. applications information
ltc2217 27 2217f layer 1 component side layer 2 gnd plane applications information
ltc2217 28 2217f applications information layer 3 gnd layer 4 gnd
ltc2217 29 2217f layer 5 gnd layer 6 bottom side applications information
ltc2217 30 2217f 12 25 26 47 48 1 2 23 36 37 vc1 vc2 vc3 vc4 vc5 ve1 ve2 ve3 ve4 ve5 u3 fin1108 3.3v en12 en34 en58 en78 en i1n i1p i2n i2p i3n i3p i4n i4p i5n i5p i6n i6p i7n i7p i8n i8p o1n o1p o2n o2p o3n o3p o4n o4p o5n o5p o6n o6p o7n o7p o8n o8p 3 22 27 46 13 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 3 22 27 46 13 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 u2 ltc2217iup sense gnd2 vcm gnd vdd5 vdd6 gnd7 ainp ainn gnd10 gnd11 encp encn gnd14 vdd15 vdd16 d11+ d11 d10+ d10 d9+ d9 d8+ d8 clkcout+ clkout d7+ d7 d8+ d8 d5+ d5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 nc rand mode lvds of+ of d15+ d15 d14+ d14 d13+ d13 d12+ d12 ognd50 ovdd49 17 18 19 20 21 22 23 24 25 26 27 27 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 vdd17 gnd18 shdn dith d0 d0+ d1 d1+ d2 d2+ d3 d3+ d4 d4+ ognd31 ovdd32 1 2 3 4 8 7 6 5 u5 fin1101k8x c15 0.1 f r41 100 rin gnd en gnd rin+ vcc dout+ dout 2217 f16 assembly *version table u2 bits c8 r45 dc996b-e ltc2217iup 16 4.7pf 86.6 dc996b-f ltc2217iup 16 1.8pf 182 dc996b-g ltc2216iup 16 4.7pf 86.6 dc996b-h ltc2216iup 16 1.8pf c9-10 8.2pf 3.9pf 8.2pf 3.9pf l1 56nh 18nh 56nh 18nh 182 r36, 44 86.6 43.2 86.6 43.2 t2 1mhz to 70mhz wbc1-1lb 1mhz to 70mhz wbc1-1lb frequency 70mhz to 140mhz 70mhz to 140mhz mabaes0060 mabaes0060 dc996b-i ltc2215iup 16 4.7pf 86.6 dc996b-j ltc2215iup 16 1.8pf 8.2pf 3.9pf 56nh 18nh 182 86.6 43.2 1mhz to 70mhz wbc1-1lb 70mhz to 140mhz mabaes0060 c5 0.01 f c7 0.01 f c12 0.1 f c6 0.01 f c4 8.2pf c3 0.01 f c13 2.2 f r14 1000 r15 5 c26 0.1 f c25 0.1 f c16 0.1 f c18 opt c19 opt r44 86.6 r11 33.2 r12 33.2 r13 100 r28 10 r16 100 r17 100 r9 10 r10 10 r27 10 c17 2.2 f v cc r37 100 c8 4.7pf r5 5.1 r4 5.1 r42 ferrite bead r43 ferrite bead r45 86.6 l1 56nh c10 8.2pf r36 86.6 r2 49.9 r1 49.9 c8 8.2pf c2 0.01 f c1 0.01 f t1 maba-007159- 000000 tp1 ext ref t2 t3 etc1-1-13 j5 ain r8 1000 r6 1000 j3 r7 1000 3.3v j7 encode clock 2 4 6 1 3 5 dither on off v cc v cc v cc shdn run 2 4 6 1 3 5 vdd gnd 2 4 6 1 3 5 r24 100k r26 4990 tp5 3.3v tp2 pwr gnd c35 0.1 f c36 0.1 f c28 0.1 f c29 0.1 f c30 0.1 f c20 0.1 f c22 0.1 f c34 0.1 f c31 0.1 f c32 0.1 f c38 4.7 f c24 4.7 f c14 4.7 f 12 25 26 47 48 1 2 23 36 37 vc1 vc2 vc3 vc4 vc5 ve1 ve2 ve3 ve4 ve5 u4 fin1108 3.3v en12 en34 en58 en78 en i1n i1p i2n i2p i3n i3p i4n i4p i5n i5p i6n i6p i7n i7p i8n i8p o1n o1p o2n o2p o3n o3p o4n o4p o5n o5p o6n o6p o7n o7p o8n o8p 5 44 43 42 41 40 39 38 35 34 33 32 31 30 29 28 45 44 43 42 41 40 39 38 35 34 33 32 31 30 29 28 r30 100 r23 100 r22 100 r21 100 r20 100 r19 100 r18 100 r31 100 r40 100 r39 100 r38 100 r35 100 r34 100 r33 100 r32 100 r29 4990 r25 4990 u1 24lc02st vcc gnd 6cl 6da wp a2 a1 a0 6 5 7 3 2 1 4 8 3.3v c27 0.1 f array eeprom r3 dnp 2 4 6 1 3 5 vdd gnd on off j4 65 j1e j1o mec8-150-02-l-d-edge_connre-dim j2 mode j9 aux pwr connector applications information
ltc2217 31 2217f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description up package 64-lead plastic qfn (9mm 9mm) (reference ltc dwg # 05-08-1705) 9 .00 0.10 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation wnjr-5 2. all dimensions are in millimeters 3. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 4. exposed pad shall be solder plated 5. shaded area is only a reference for pin 1 location on the top and bottom of package 6. drawing not to scale pin 1 top mark (see note 5) 0.40 0.10 64 63 1 2 bottom view?xposed pad 7.15 0.10 7.15 0.10 7.50 ref (4-sides) 0.75 0.05 r = 0.10 typ r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ?0.05 (up64) qfn 0406 rev c recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 7.50 ref (4 sides) 7.15 0.05 7.15 0.05 8.10 0.05 9.50 0.05 0.25 0.05 0.50 bsc package outline pin 1 chamfer c = 0.35
ltc2217 32 2217f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 0108 ? printed in usa related parts part number description comments ltc1749 12-bit, 80msps wideband adc up to 500mhz if undersampling, 87db sfdr ltc1750 14-bit, 80msps wideband adc up to 500mhz if undersampling, 90db sfdr lt1993 high speed differential op amp 600mhz bw, 75dbc distortion at 70mhz ltc2202 16-bit, 10msps adc 150mw, 81.6db snr, 100db sfdr ltc2203 16-bit, 25msps adc 230mw, 81.6db snr, 100db sfdr ltc2204 16-bit, 40msps adc 470mw, 79db snr, 100db sfdr ltc2205 16-bit, 65msps adc 530mw, 79db snr, 100db sfdr ltc2206 16-bit, 80msps adc 725mw, 77.9db snr, 100db sfdr ltc2207 16-bit, 105msps adc 900mw, 77.9db snr, 100db sfdr ltc2208 16-bit, 130msps adc 1250mw, 77.7db snr, 100db sfdr ltc2209 16-bit, 160msps adc 1450mw, 77.1db snr, 100db sfdr ltc2215 16-bit, 65msps adc 700mw, 81.5db snr, 100db sfdr ltc2216 16-bit, 80msps adc 970mw, 81.3db snr, 100db sfdr ltc2220 12-bit, 170msps adc 890mw, 67.5db snr, 9mm 9mm qfn package ltc2220-1 12-bit, 185msps adc 910mw, 67.5db snr, 9mm 9mm qfn package ltc2249 14-bit, 65msps adc 230mw, 73db snr, 5mm 5mm qfn package ltc2250 10-bit, 105msps adc 320mw, 61.6db snr, 5mm 5mm qfn package ltc2251 10-bit, 125msps adc 395mw, 61.6db snr, 5mm 5mm qfn package ltc2252 12-bit, 105msps adc 320mw, 70.2db snr, 5mm 5mm qfn package ltc2253 12-bit, 125msps adc 395mw, 70.2db snr, 5mm 5mm qfn package ltc2254 14-bit, 105msps adc 320mw, 72.5db snr, 5mm 5mm qfn package ltc2255 14-bit, 125msps adc 395mw, 72.4db snr, 5mm 5mm qfn package ltc2299 dual 14-bit, 80msps adc 445mw, 73db snr, 9mm 9mm qfn package lt5512 dc-3ghz high signal level downconverting mixer dc to 3ghz, 21dbm iip3, integrated lo buffer lt5514 ultralow distortion if ampli? er/adc driver with digitally controlled gain 450mhz 1db bw, 47db oip3, digital gain control 10.5db to 33db in 1.5db/step lt5522 600mhz to 2.7ghz high linearity downconverting mixer 4.5v to 5.25v supply, 25dbm iip3 at 900mhz, nf = 12.5db, 50 1 single-ended rf and lo ports

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